I am a graduate student at UC Santa Cruz pursuing a MS in Computer Engineering. I work in the Vertical Architectures, Memories, and Algorithms (VAMA) group, part of the Hardware Systems Collective.
Previously, I was an undergraduate at UC Santa Cruz, affiliated with Crown College. I majored in Computer Engineering with a minor in Electrical Engineering, class of 2019.
I worked as a Teaching Assistant for CSE 120 (Computer Architecture) and for CSE 100/L (Logic Design). I have also worked as a Student Consultant at the Faculty Instructional Technology Center for ITS Learning Technologies.
You can view my resumé here. Or, if you prefer, my LinkedIn.
Edulog is a novel hardware design language targeted towards beginners. It was designed as the class project for my programming languages class. Together with my colleague Amogh Lonkar we designed the syntax, and wrote a parser for it. It translates the input design into FIRRTL to enable interoperability with many different tools, and with the option of generating Verilog if desired. The entire project is written in Scala.
I wrote a Notepad++ UDL to syntax highlight FIRRTL files. You can get it here.
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